Yes, I never spent much time thinking about it; but if you join base and collector, then for a given current, the current through the base will reduce by the gain of the transistor, which could be as much as, say, 50 as the transistor is not actually quite saturated. This should result in the base emitter junction voltage being much lower down the curve. So I was puzzled to see your experimental results. I didn't want to comment on them as I don't currently have time to set this up here, but since you mentioned it...
BTW, your spell checker has been changing 'the' to 'thee' for quite some time now.
Yes, I never spent much time thinking about it; but if you join base and collector, then for a given current, the current through the base will reduce by the gain of the transistor, which could be as much as, say, 50 ...
I think what you may be overlooking is that, once one is beyond a pretty low Ib threshold (typically 5-10mA for a small signal transistor), Vbe changes little with changes in Ib.
So I was puzzled to see your experimental results. I didn't want to comment on them as I don't currently have time to set this up here, but since you mentioned it...
I'd certainly be interested to see if you can reproduce my findings, either by experimentation or simulation, but it's difficult to see what I could have done wrong!
As I wrote,once I started 'thinking straight' I realised that saturation can never occur with base and collector connected. Hence, this ....
... can never saturate,even if R2 = 0, since Vce cannot be less than Vbe (since it is equal to {or greater than,if R2>0} Vbe) - but, on the other hand, with this second arrangement saturation will occur if Vce falls to below Vbe (which changes little as Vce falls) ...
No,it's not my spell checker, it's my keyboard. Pressing thee "e" key results in anything from one to five "e" characters appearing! My eyes and/or spell checker are catching (and correcting) most of these events, but some are being missed
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